1. Field of the Invention
The present invention relates to a semiconductor device structure and a processing method thereof for preventing plasma-induced-damage to the device during plasma processing. More particularly, the present invention is directed to a MOSFET semiconductor device structure and a processing method thereof for preventing plasma-induced-damage to the gate oxide during high-density plasma deposition of an interlayer dielectric layer.
2. Description of the Related Art
As ultra large scale integration (ULSI) technology has progressed, the use of plasma processes for etching and deposition has increased. Plasma deposition is a preferred process because it offers a good thermal budget control due to a low process temperature. Plasma deposition and etching offer a high directionality that can result in high gap-fill capability during deposition. A plasma process inherently produces photons. When these photons are absorbed by the gate oxide, they induce damage. This damage is called plasma-induced-damage (PID). The PID degrades gate oxide reliability and may increase the probability of device failure. The PID in gate oxide leads to gate leakage current.
Though the PID to the gate oxide has been considered acceptable in the past, recently, due to the use of thinner gate oxides and use of high-density plasma (HDP) deposition and etching techniques, a substantial amount of PID is generated in the gate oxide, and accordingly additional consideration to avoid or minimize the PID damage to the gate oxide is necessary. The HDP deposition and etching processes are associated with greater amounts of photons, which in turn has the potential of more easily penetrating through the various layers of gate stack, and thereby inflicting more damage to the gate oxide. In fact, an amount of photons associated with the HDP may be sufficient to overcome the protection to the gate stack provided by a photon-absorbing layer formed on the gate stack. At present, the HDP process is widely used for interlayer dielectric layer deposition on the gate structures. Hence, the PID to the gate oxide layer in this process needs to be eliminated or minimized to obtain high device performance. The PID problem of the gate oxide layer is explained below, more clearly, with reference to FIGS. 1 and 2.
FIG. 1 illustrates the structure of a conventional MOS transistor. An isolation region 15, a gate oxide layer 20, a gate conductive layer 25, and a gate hard mask 30 are formed on a silicon substrate 10. The hard mask layer 30, the gate conductive layer 25, and the gate oxide layer 20 are patterned and these three layers together form a gate structure (G). A shallow lightly doped portion of the source/drain regions 40a and 40b is formed by ion-implantation. Next, a gate spacer 35 is formed on the gate structure (G). Then, impurities are implanted into the substrate to form heavily doped deep portions of the source/drain regions 40a and 40b of the MOS transistor. Next, an etch stop layer 45 is formed on the resultant structure. The etch stop layer 45 is formed to protect the active surface of source/drain regions 40a and 40b, and contact holes are formed by etching through an interlayer dielectric layer 50 formed in the next step.
Conventionally, the etch stop layer 45 is made of silicon oxy-nitride (SiON) or silicon nitride (SiN). Next, an interlayer dielectric layer 50 is deposited on the etch stop layer 45. A HDP process is used to form the interlayer dielectric material in a narrow space between adjacent gate structures (G). The HDP process, however, has a problem in that it generates photons at a high density level. As a result, the photons are absorbed into the gate oxide layer 20 during the interlayer dielectric layer 50 deposition process, and a gate leakage current is generated.
The gate leakage current problem is explained more specifically with reference to FIG. 2. FIG. 2 illustrates a gate current variation with the gate voltage, with no bias connected to the source/drain terminals, and when interlayer dielectric layer 50 is formed with or without using the HDP process. After the HDP deposition process, when a voltage is applied to the gate conductive layer 25, a leakage current is generated in the gate oxide 20. In FIG. 2, a plot designated with label â shows a leakage current (lg) in the gate oxide 20 when the interlayer dielectric layer 50 is deposited without using the HDP process. Plots designated with labels {circumflex over (b)} and ĉ show higher leakage currents in the gate oxide, as compared to the plot â, when the interlayer dielectric layer 50 is deposited using the HDP process. For the plot labeled ĉ, a longer HDP process time is used (hence, many more photons are generated) than that of {circumflex over (b)}. The longer HDP process time resulted in a higher gate leakage current in plot ĉ as compared to plot {circumflex over (b)}. This phenomenon of increased leakage current of the gate oxide with exposure to a plasma process is plasma induced damage (PID).
A wavelength of photons generated during the HDP process is in a range of 300–800 nm, as illustrated in FIG. 3. An etching stop layer 45 made of SiN does not easily absorb photons having a wavelength higher than 300 nm. The extinction coefficient k of silicon nitride is nonzero for wavelengths below 200 nm, peaking at 1.5 for wavelengths around 100 nm. The k value of silicon nitride is essentially zero (0) for wavelengths greater than 200 nm. The k value of SiO2 is essentially zero (0) for wavelengths greater than about 200 nm. For SiON, which is a mixture of SiO2 and SiN, the k value is expected to be zero for wavelengths greater than 200 nm. Hence, silicon nitride or SiON, when used for forming the etch stop layer 45, are ineffective in absorbing photons with wavelengths greater than 200 nm, and protecting the gate oxide layer 20 against PID during HDP deposition of the interlayer dielectric layer 50. Due to the above reasons a new approach is desired to prevent or minimize the PID of the gate oxide layer 20, during HDP deposition of the interlayer dielectric layer 50.